1. Field of the Invention
The present invention relates to digital electronics. In particular, the present invention relates to clock signal synthesizer circuits, ring oscillator circuits, delay circuits and phase locked loop digital circuits.
2. Description of the Prior Art and Related Information
Circuits used to generate a high frequency periodic signal are employed in a wide variety of applications, for example, in computer, video and other applications. One example of a computer application is in a microprocessor clock generation circuit. An example of a video application is in a pixel clock generation circuit. Another video application is in a memory clock generation circuit. These two video applications may both be required in a single video graphics board. Furthermore, video graphics boards may need to be compatible with several applications, each requiring different frequency clock signals. Therefore, conventionally a large number of clock signal generation chips would be required for such a video graphics board. Also, such applications may require extremely high frequency periodic signals, for example, 14 MHz or greater. Providing such high frequency signals presents difficult stability and accuracy problems due to inherent limitations in the switching speed of the component transistors.
One approach to providing plural high frequency clock signals employs a phase locked loop (PLL) circuit and a reference clock signal to derive several clock signals from the reference clock signal See, e.g., Jeong, et al., "Design of PLL-Based Clock Generation Circuits," IEEE J. of Sol. State Cir., Vol. SC-22, No. 2, Apr. 1987. A critical component of such PLL based clock signal synthesizer circuit designs, in turn, is a ring oscillator circuit which generates a periodic signal from a control current input. At very high frequencies it is often the failure of such ring oscillator circuits to provide linear response to a control current which limits the accuracy of the clock signal synthesizer circuit.
A conventional ring oscillator circuit design is illustrated schematically in FIG. 1. As shown therein, the basic construction of such a ring oscillator includes an odd number of inverting delay stages, delay stages 1.sub.1 -1.sub.N, arranged in series in a ring configuration. A simple tracing of a DC signal through the ring oscillator of FIG. 1 will show that a periodic signal is generated at the output, the output signal having a frequency of 1/2NT, where T is the delay of each inverting stage and N is the number of stages. The delay of each stage in turn is controlled by the control signal, illustrated as dashed lines 2 in FIG. 1, which signal is typically a control current. The control current is in turn provided to each of the inverter gates 3.sub.1 -3.sub.N, as illustrated by the current source symbols for each stage. This control current controls the switching speed of each inverter and hence the delay of each stage 1.sub.1 -1.sub.N. In cases where the control current is provided by a voltage to current converter from a control voltage, the overall arrangement is referred to as a voltage controlled oscillator (VCO).
Since the ring oscillator is designed to provide a stable output frequency which varies as a function of the input control signal, it is desirable that the amount of delay be a linear function of the control signal. This linearity is approximately satisfied for conventional ring oscillator circuits at lower frequencies. As the frequency increases, however, transient effects due to the switching of the inverter gates 3.sub.1 -3.sub.N introduce significant nonlinearities, rendering the amount of delay a less predictable function of the control current.
Referring to FIG. 2, a conventional delay stage 1 employs a CMOS inverter including p-channel and n-channel switching field effect transistors, 4 and 5, respectively. These switching transistors 4, 5 receive an input signal on the gates thereof provided from the preceding stage in the ring configuration. Switching transistors 4, 5 are coupled to V.sub.DD and ground, respectively, through transistors 6 and 7. Transistors 6, 7 are biased via diode connected p-channel and n-channel transistors 8 and 9, respectively. This configuration results in control bias voltages V.sub.P and V.sub.N applied to the gate of transistors 6 and 7, respectively, to control their respective resistances so as to mirror current I through these transistors. The magnitude of the current I through these transistors 6 and 7, in turn will control the overall delay of the stage by determining the time it takes to charge the capacitance C.sub.L of the output load (typically the parasitic capacitance of the next stage in the ring configuration). Also illustrated in FIG. 2 are the parasitic capacitance C.sub.PP of p-channel transistors 4 and 6 and the parasitic capacitance C.sub.PN of n-channel transistors 5 and 7. These parasitic p-channel and n-channel capacitances, C.sub.PP and C.sub.PN, result in non-linearity of the delay stage at high frequency operation.
More specifically, the delay of the stage will essentially be the time it takes to charge the load capacitance C.sub.L by the current I. At lower operation frequencies, the switching speed of the transistors 4, 5 will be relatively negligible relative to the charge time of the output load capacitance C.sub.L and therefore transient effects may be ignored and current I to the output treated as constant. At high frequencies, however, the transient effects become significant. In particular, the charging or discharging of the parasitic capacitances C.sub.PP and C.sub.PN cause significant fluctuations in the current flow. Hence, the time to charge C.sub.L, and thus the overall delay time of the delay stage, is subject to fluctuations.
For example, as illustrated in FIG. 2, consider a transition of the input signal from V.sub.DD to ground. At the beginning of the transition, the voltage on the capacitor C.sub.L is 0 volts and the p-channel parasitic capacitor C.sub.PP is charged to V.sub.DD, As the input transitions from V.sub.DD, to 0, the charge on C.sub.L and the parasitic capacitance C.sub.PP are shared, and the rate of voltage change is initially a function of C.sub.L, C.sub.PP and the on resistance of the p-channel transistors 4 and 6. Then, as the bias transistor 6 moves to saturation, the transistor 6 behaves like a current source with a current I set by the bias voltage V.sub.P. Therefore, the delay of the stage through this transition period is a highly unpredictable and nonlinear. Since the relative effect of these parasitic capacitances increases with frequency, the amount of delay in response to a control current may be quite nonlinear at high frequencies. Additionally, these parasitic capacitances and the resistance of switching transistors are highly process dependent and hence the delay may vary strongly from batch to batch. This will in turn introduce instabilities into tee entire frequency generation circuit and make reliable generation of very high frequency clock signals impossible.
Accordingly, a need presently exists for a periodic signal generation circuit capable of reliably and accurately generating high frequency periodic signals A need further exists for a ring oscillator circuit which has a frequency which is a substantially linear function of the control current applied thereto, even at high frequencies. Additionally, a need presently exists for an improved delay stage suitable for use in such a ring oscillator or other applications where a controllable delay is required.